MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 151

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

If the FINT bit is set, a fault condition resulting in setting the FFLAG bit will also latch a CPU interrupt
request. The interrupt request latch is not cleared until one of these actions occurs:
If prior to a vector fetch, the interrupt request latch is cleared by one of the actions listed, a CPU interrupt
will no longer be requested. A vector fetch does not alter the state of the PWMs, the FFLAG event flag,
or FINT.
15.5.1.2 Manual Mode
In manual mode, the PWM(s) are disabled immediately once a fault condition is detected (logic high). The
PWM(s) remain disabled until software clears the FFLAG event bit and a new PWM cycle begins. A fault
condition on the pin can only be cleared, allowing the PWM(s) to enable, if a logic low level at the fault pin
is present at the start of a PWM cycle. See
The function of the fault control and event bits is the same as in automatic mode except that the PWMs
are not re-enabled until the FFLAG event bit is cleared by writing to the FTACK bit and the fault condition
is cleared (logic low).
15.5.2 Software Output Disable
Setting PWM disable bit DIS0 or DIS1 in PWM control register 1 immediately disables the corresponding
PWM pins. The PWM pin(s) remain disabled until the PWM disable bit is cleared and a new PWM cycle
begins as shown in
Figure
flags associated with the PWM disable bits.
Freescale Semiconductor
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The FFLAG bit is cleared by writing a 1 to the corresponding FTACK bit.
The FINT bit is cleared. This will not clear the FFLAG bit.
A reset automatically clears the interrupt latch.
15-13. Setting a PWM disable bit does not latch a CPU interrupt request, and there are no event
If the FFLAG or FINT bits are not cleared during the interrupt service
routine, the interrupt request latch will not be cleared.
FAULT PIN 2 OR 4
PWM(S) ENABLED
Figure 15-12. PWM Disabling in Manual Mode
MC68HC908LB8 Data Sheet, Rev. 1
FFLAGX CLEARED
Figure
NOTE
PWM(S) DISABLED
15-12.
PWM(S) ENABLED
Fault Protection
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