MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 170

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Resets and Interrupts
16.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
16.3.2.3 IRQ Pin
A logic 0 on the IRQ pin latches an external interrupt request when pin PTC2/SHTDWN/IRQ is configured
as a software interrupt.
16.3.2.4 Timer Interface Module (TIM)
TIM CPU interrupt sources:
16.3.2.5 KBD0–KBD6 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt request.
16.3.2.6 Analog-to-Digital Converter (ADC)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
16.3.2.7 Pulse-Width Modulator with Fault Input (PWM)
PWM CPU interrupt sources:
16.3.2.8 High Resolution PWM (HRP)
When the SHTIE bit is set, the HRP module is capable of generating a CPU interrupt on detection of a
falling edge or a low level on the SHTDN pin.
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TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after
matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and
control register.
TIM channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM CPU
interrupt requests. CHxF and CHxIE are in the TIM channel x status and control register.
Fault pin interrupt (FAULT) — When the FINT bit is set, the PWM module is capable of generating
a CPU interrupt on detection of a rising edge on the FAULT pin.
PWM interrupt (PWMINT) — When the PWMINT bit is set, the PWM module is capable of
generating a CPU interrupt when the PWM reload flag (PWMF) is set. The PWMF bit is set at the
beginning of every reload cycle.
A software interrupt pushes PC onto the stack. An SWI does not push PC
– 1, as a hardware interrupt does.
MC68HC908LB8 Data Sheet, Rev. 1
NOTE
Freescale Semiconductor