C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 162
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C8051F537-IM
Manufacturer Part Number
C8051F537-IM
Description
IC 8051 MCU 2K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1400
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F52x/F52xA/F53x/F53xA
Table 16.1. SPI Slave Timing Parameters
162
Master Mode Timing* (See Figure 16.6 and Figure 16.7)
Slave Mode Timing* (See Figure 16.8 and Figure 16.9)
Note: T
Parameter
T
T
T
T
T
T
T
T
T
T
MCKH
T
MCKL
T
T
CKH
CKL
SOH
SEZ
SDZ
MIS
MIH
SIS
SIH
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
SE
SD
SYSCLK
is equal to one period of the device system clock (SYSCLK) in ns.
SCK High Time
SCK Low Time
MISO Valid to SCK Sample Edge
SCK Sample Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Description
Rev. 1.3
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
Min
20
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
0
4 x T
4 x T
4 x T
Max
—
—
—
—
—
—
SYSCLK
SYSCLK
—
—
—
—
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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