C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 177

• Manufacturer Part Number: C8051F537-IM
• Description: IC 8051 MCU 2K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1400

SFR Definition 17.13. LIN0ST: LIN0 STATUS Register
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ACTIVE
Bit7
R
ACTIVE: LIN Bus Activity Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
IDLTOUT: Bus Idle Timeout Bit (slave mode only).
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep mode.
ABORT: Aborted transmission signal (slave mode only).
0: The current transmission has not been interrupted or stopped. This bit is reset to 0 after
receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP bit
(LIN0CTRL.7) has been set.
DTREQ: Data Request bit (slave mode only).
0: Data identifier has not been received.
1: Data identifier has been received.
LININT: Interrupt Request bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
ERROR: Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
WAKEUP: Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received.
DONE: Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the start of
a transmission.
1: The current transmission is complete.
IDLTOUT
Bit6
R
ABORT
Bit5
R
DTREQ
Bit4
C8051F52x/F52xA/F53x/F53xA
R
Rev. 1.3
LININT
R/W
Bit3
ERROR WAKEUP
Bit2
R
Bit1
R
DONE
Bit0
Address: 0x09 (indirect)
R
Reset Value
00000000
177