C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 176

• Manufacturer Part Number: C8051F537-IM
• Description: IC 8051 MCU 2K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1400

C8051F52x/F52xA/F53x/F53xA
SFR Definition 17.12. LIN0CTRL: LIN0 Control Register
176
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
STOP
Bit7
W
STOP: Stop Communication Processing Bit (slave mode only).
This bit is to be set by the application to block the processing of the LIN Communications
until the next SYNCH BREAK signal. It is used when the application is handling a data
request interrupt and cannot use the frame content with the received identifier (always reads
0).
SLEEP: Sleep Mode Warning.
This bit is to be set by the application to warn the peripheral that a Sleep Mode Frame was
received and that the Bus is in sleep mode or if a Bus Idle timeout interrupt is requested.
The application must reset it when a Wake-Up interrupt is requested.
TXRX: Transmit/Receive Selection Bit.
This bit determines if the current frame is a transmit frame or a receive frame.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
DTACK: Data acknowledge bit (slave mode only).
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit will auto-
matically be cleared to 0 by the LIN controller.
RSTINT: Interrupt Reset bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
RSTERR: Error Reset Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
WUPREQ: Wake-Up Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automatically be
cleared to 0 by the LIN controller.
STREQ: Start Request Bit (master mode only).
1: Start a LIN transmission. This should be set only after loading the identifier, data length
and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
SLEEP
Bit6
W
TXRX
Bit5
W
DTACK
R/W
Bit4
RSTINT
Rev. 1.3
R/W
Bit3
RSTERR WUPREQ
R/W
Bit2
R/W
Bit1
STREQ
R/W
Bit0
Address: 0x08 (indirect)
Reset Value
00000000