C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 65

• Manufacturer Part Number: C8051F537-IM
• Description: IC 8051 MCU 2K FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-QFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1400

SFR Definition 4.5. ADC0CF: ADC0 Configuration
Note: Round the result up.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Bit0:
R/W
Bit7
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 2.3 on page 29.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the Burst Mode Oscillator, specified in Table 2.3.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
GAINEN: Gain Enable Bit.
Controls the gain programming. For more information of the usage, refer to the following
chapter: Section “4.4. Selectable Gain” on page 60.
AD0SC
R/W
Bit6
=
------------------- - 1
CLK
AD0SC
FCLK
R/W
Bit5
SAR
–
*
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
or
Rev. 1.3
R/W
Bit3
CLK
SAR
R/W
Bit2
=
AD0RPT
----------------------------
AD0SC
FCLK
R/W
Bit1
+
1
GAINEN
R/W
Bit0
SFR Address:
Reset Value
11111000
0xBC
65