HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 236

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 13 Timer Z
13.3.9
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
Rev. 1.00 Sep. 16, 2005 Page 206 of 490
REJ09B0216-0100
Bit
7
6
5
4
3
2
1
0
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
When GR functions as input capture, TCNT is cleared by input capture.
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter Clear 2 to 0
000: Disables TCNT clearing
001: Clears TCNT by GRA compare match/input
010: Clears TCNT by GRB compare match/input
011: Synchronization clear; Clears TCNT in synchronous
100: Disables TCNT clearing
101: Clears TCNT by GRC compare match/input
110: Clears TCNT by GRD compare match/input
111: Synchronization clear; Clears TCNT in synchronous
Clock Edge 1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Time Prescaler 2 to 0
000: Internal clock: count by φ
001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Description
capture*
capture*
with counter clearing of the other channel’s timer*
capture*
capture*
with counter clearing of the other channel’s timer*
1
1
1
1
2
2