HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 246

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Section 13 Timer Z
1. Free-running count operation and periodic count operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The GR registers for setting the period are designated
as output compare registers, and counter clearing by compare match is selected by means of bits
CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment
operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count
value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and
TCNT is cleared to H'0000.
If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point,
the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation
again from H'0000.
Figure 13.9 illustrates periodic counter operation.
Rev. 1.00 Sep. 16, 2005 Page 216 of 490
REJ09B0216-0100
Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as free-
running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter
starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag
in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point,
timer Z requests an interrupt. After overflow, TCNT starts an increment operation again from
H'0000.
Figure 13.8 illustrates free-running counter operation.
H'FFFF
H'0000
STR0,
STR1
OVF
TCNT value
Figure 13.8 Free-Running Counter Operation
Time

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