HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 78

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 3 Exception Handling
3.2.3
IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 1.00 Sep. 16, 2005 Page 48 of 490
REJ09B0216-0100
Bit
7
6
5
4
3
2
1
0
Bit Name
IENDT
IENTA
IENWP

IEN3
IEN2
IEN1
IEN0
Interrupt Enable Register 1 (IENR1)
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
Description
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
RTC Interrupt Enable
When this bit is set to 1, RTC interrupt requests are
enabled.
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
Reserved
This bit is always read as 1.
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3 pin
are enabled.
IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2 pin
are enabled.
IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1 pin
are enabled.
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0 pin
are enabled.