HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 79

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2.4
IENR2 enables, timer B1 overflow interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
3.2.5
IRR1 is a status flag register for direct transition interrupts, RTC interrupts, and IRQ3 to IRQ0
interrupt requests.
Bit
7, 6
5
4 to 0
Bit
7
Bit Name

IENTB1

Bit Name
IRRDT
Interrupt Enable Register 2 (IENR2)
Interrupt Flag Register 1 (IRR1)
Initial
Value
All 0
0
All 1
Initial
Value
0
R/W

R/W

R/W
R/W
Description
Reserved
These bits are always read as 0.
Timer B1 Interrupt Enable
When this bit is set to 1, timer B1 overflow interrupt
requests are enabled.
Reserved
These bits are always read as 1.
Description
Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
Rev. 1.00 Sep. 16, 2005 Page 49 of 490
Section 3 Exception Handling
REJ09B0216-0100