HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 69

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Prior to executing BSET instruction
• BSET instruction executed instruction
• After executing BSET instruction
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
Input/output
Pin state
PCR5
PDR5
Input/output
Pin state
PCR5
PDR5
BSET
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
#0,
P57
Input
Low
level
0
1
P57
Input
Low
level
0
0
@PDR5
0
0
0
P56
Input
High
level
P56
Input
High
level
1
P55
Output
Low
level
1
0
P55
Output
Low
level
1
0
The BSET instruction is executed for port 5.
P54
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P53
Output
Low
level
1
0
Rev. 1.00 Sep. 16, 2005 Page 39 of 490
P52
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P51
Output
Low
level
1
0
REJ09B0216-0100
Section 2 CPU
P50
Output
Low
level
1
0
P50
Output
High
level
1
1