HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 355

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
5
4
3
2
1
0
Bit Name
MST
TRS
CKS3
CKS2
CKS1
CKS0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Master/Slave Select
Transmit/Receive Select
In master mode with the I
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1. If an overrun error
occurs in master mode with the clock synchronous serial
format, MST is cleared to 0 and slave receive mode is
entered.
Operating modes are described below according to MST
and TRS combination. When clock synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
These bits should be set according to the necessary
transfer rate (see table 17.2) in master mode. In slave
mode, these bits are used for reservation of the setup
time in transmit mode. The time is 10 t
and 20 t
cyc
when CKS3 = 1.
Rev. 1.00 Sep. 16, 2005 Page 325 of 490
Section 17 I
2
C bus format, when arbitration
2
C Bus Interface 2 (IIC2)
cyc
when CKS3 = 0
REJ09B0216-0100