HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 379

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer:
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HD64F36077GHV
Manufacturer:
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Quantity:
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17.4.7
The signal levels on the SCL and SDA pins are internally latched via the noise filter. Figure 17.16
shows a block diagram of the noise filter circuit.
The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When both outputs of the latches match, its level is output
to other blocks by the match detector. If they do not match, the previous value is held.
17.4.8
Flowcharts in respective modes that use the I
SCL or SDA
input signal
Sampling
clock
Noise Filter
Example of Use
Sampling clock
D
System clock
Figure 17.16 Block Diagram of Noise Filter
Latch
cycle
C
Q
D
2
C bus interface are shown in figures 17.17 to 17.20.
Latch
C
Q
Rev. 1.00 Sep. 16, 2005 Page 349 of 490
Match detector
Section 17 I
2
C Bus Interface 2 (IIC2)
SCL or SDA
Internal
REJ09B0216-0100
signal

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