HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 333

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5
Figure 16.9 shows the general format for clock synchronous communication. In clock synchronous
mode, data is transmitted or received synchronous with clock pulses. A single character in the
transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial
communication, data on the transmission line is output from one falling edge of the
synchronization clock to the next. In clock synchronous mode, the SCI3 receives data in
synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit
is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex
communication through the use of a common clock. Both the transmitter and the receiver also
have a double-buffered structure, so data can be read or written during transmission or reception,
enabling continuous data transfer.
16.5.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
16.5.2
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 16.4.
Operation in Clock Synchronous Mode
Clock
SCI3 Initialization
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Figure 16.9 Data Format in Clock Synchronous Communication
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Bit 3
Section 16 Serial Communication Interface 3 (SCI3)
8-bit
Bit 4
Rev. 1.00 Sep. 16, 2005 Page 303 of 490
Bit 5
Bit 6
MSB
Bit 7
Don’t care
REJ09B0216-0100
*