DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 156

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6010A/6015
21.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
FIGURE 21-3:
FIGURE 21-4:
DS70150D-page 156
PWRT Time-out
PWRT Time-out
OST Time-out
Internal Reset
OST Time-out
Internal Reset
DD
Internal POR
Internal POR
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
1.85V.
MCLR
MCLR
V
V
DD
DD
The
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
device
supply
POR
), which is
T
T
OST
OST
voltage
T
PWRT
T
PWRT
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock, and the PC will
jump to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
PWRT
© 2008 Microchip Technology Inc.
DD
) is applied. The T
)
POR
DD
): CASE 1
+ T
POR
PWRT
, which is
. When
PWRT