DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 221

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPENDIX A:
Revision A (July 2005)
Original data sheet for dsPIC30F6010A/6015 devices.
Revision B (September 2006)
This revision reflects updates in these areas:
• Data Ram protection feature enables segments of
• BSRAM and SSRAM SFRs added to support
• Base Instruction CP1 removed (see Table 22-2)
• Supported I
• Revised Electrical Characteristics:
• Added note to package drawings.
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
© 2008 Microchip Technology Inc.
RAM to be protected when used in conjunction
with Boot and Secure Code Segment Security
(see Section 3.2.7 “Data Ram Protection Fea-
ture”)
Data Ram Protection (see Table 3-3)
- Operating current (I
- Idle current (I
- Power-down current (I
- I/O Pin input specifications (see Table 24-9)
- BOR voltage limits (see Table 24-11)
- Watchdog Timer time-out limits (see
Table 24-6)
Table 24-7)
Table 24-8)
Table 24-21)
2
C Slave addresses (see Table 17-2)
IDLE
) specifications (see
REVISION HISTORY
DD
) specifications (see
PD
) specifications (see
dsPIC30F6010A/6015
Revision D (June 2008)
This revision reflects these updates:
• Changed the location of the input reference in the
• Added FUSE Configuration Register (FICD)
• Removed erroneous statement regarding genera-
• Electrical Specifications:
• Additional minor corrections throughout the
10-bit High-Speed ADC Functional Block Diagram
(see Figure 20-1)
details (see Section 21.6 “Device Configuration
Registers” and Table 21-9)
tion of CAN receive errors (see Section 19.4.5
“Receive Errors”)
- Resolved TBD values for parameters DO10,
- 10-bit High-Speed ADC t
- Parameter OS65 (Internal RC Accuracy) has
- Parameter DC12 (RAM Data Retention Volt-
- Parameter D134 (Erase/Write Cycle Time)
- Removed parameters OS62 (Internal FRC
- Parameter OS63 (Internal FRC Accuracy)
- Updated Min and Max values and Conditions
document
DO16, DO20, and DO26 (see Table 24-10)
ter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table 24-41)
been expanded to reflect multiple Min and
Max values for different temperatures (see
Table 24-19)
age) Min and Max values have been updated
(see Table 24-5)
has been updated to include Min and Max
values and the Typ value has been removed
(see Table 24-12)
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 24-18)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 24-18)
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for parame-
ter SY20 (see Table 24-21)
PDU
timing parame-
DS70150D-page 221