DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 50

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6010A/6015
6.4
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program
32 instructions at one time.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The addresses loaded must always be from a 32
address boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and 32 TBLWTH instructions are required to
load the 32 instructions.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written.
After the latches are written, a programming operation
needs to be initiated to program the data.
The Flash program memory is readable, writable and
erasable during normal operation over the entire V
range.
DS70150D-page 50
RTSP Operation
DD
6.5
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
6.5.1
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
start of the programming cycle.
6.5.2
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6.5.3
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register
captures the EA<23:16> of the last table instruction
that has been executed.
6.5.4
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note:
RTSP Control Registers
NVMCON REGISTER
NVMADR REGISTER
NVMADRU REGISTER
NVMKEY REGISTER
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
© 2008 Microchip Technology Inc.