DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 98

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6010A/6015
15.1.4
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR
register is equal to zero, as well as each time a period
match occurs. The postscaler selection bits have no
effect in this mode of the timer.
The Double Update mode provides two additional
functions to the user. First, the control loop bandwidth
is doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical
center-aligned PWM waveforms can be generated,
which are useful for minimizing output waveform
distortion in certain motor control applications.
15.1.5
The input clock to PTMR (F
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
PTMR is not cleared when PTCON is written.
15.1.6
The match output of PTMR can optionally be
post-scaled through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
PTMR is not cleared when PTCON is written.
15.2
PTPER is a 15-bit, double-buffered register that sets the
counting period for the PWM time base. The PTPER
buffer is loaded into the PTPER register at these instants:
• Free-Running and Single-Shot modes: When the
• Up/Down Counting modes: When the PTMR
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
The
Equation 15-1:
DS70150D-page 98
Note:
PTMR register is reset to zero after a match with
the PTPER register.
register is zero.
PWM
PWM Period
DOUBLE UPDATE MODE
Programming a value of 0x0001 in the
Period
continuous interrupt pulse, and hence,
must be avoided.
PWM TIME BASE PRESCALER
PWM TIME BASE POSTSCALER
period
register
can
be
OSC
could
determined
/4), has prescaler
generate
using
a
EQUATION 15-1:
If the PWM time base is configured for one of the
Up/Down Count modes, the PWM period will be given
by Equation 15-2.
EQUATION 15-2:
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-3:
EQUATION 15-3:
15.3
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate Duty Cycle
register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the Duty Cycle register
matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the
output on the PWM pin will be active for the entire
PWM period if the value in the Duty Cycle register is
greater than the value held in the PTPER register.
FIGURE 15-2:
PTPER
0
Resolution =
Edge-Aligned PWM
T
T
Duty Cycle
PWM
PTMR
Value
PWM
=
Period
=
T
(PTMR Prescale Value)
CY
(PTMR Prescale Value)
T
PWM PERIOD
PWM PERIOD FOR
UP/DOWN COUNT
PWM RESOLUTION
EDGE-ALIGNED PWM
CY
© 2008 Microchip Technology Inc.
log (2
• 2 •
•
New Duty Cycle Latched
(PTPER + 1)
log (2)
•
(PTPER + 0.75)
T
PWM
/T
CY
)