DSPIC30F6010AT-20E/PT Microchip Technology, DSPIC30F6010AT-20E/PT Datasheet - Page 227

• Manufacturer Part Number: DSPIC30F6010AT-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010AT-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Requirements
Timing Specifications
Traps .................................................................................. 43
U
UART
© 2008 Microchip Technology Inc.
Time-out Sequence on Power-up (MCLR
Not Tied to V
Time-out Sequence on Power-up (MCLR
Tied to V
TimerQ (QEI Module) External Clock ...................... 196
Timer1, 2, 3, 4, 5 External Clock .............................. 194
10-bit High-Speed A/D Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 0, SSRC = 000) ................... 214
10-bit High-Speed A/D Conversion (CHPS = 01,
SAMC = 00001) ....................................................... 215
Input Capture ........................................................... 197
Band Gap Start-up Time Requirements ................... 193
CAN I/O Requirements ............................................ 211
CLKOUT and I/O Characteristics ............................. 191
CLKOUT and I/O Requirements .............................. 191
External Clock Requirements .................................. 187
Internal Clock Examples .......................................... 189
I
I
Motor Control PWM Requirements .......................... 199
Output Compare Requirements ............................... 197
PLL Clock ................................................................. 188
PLL Jitter .................................................................. 188
QEI External Clock Requirements ........................... 196
QEI Index Pulse Requirements ................................ 201
Quadrature Decoder Requirements ......................... 200
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ................................................ 193
Simple OC/PWM Mode Requirements .................... 198
SPI Master Mode (CKE = 0) Requirements ............. 202
SPI Master Mode (CKE = 1) Requirements ............. 203
SPI Slave Mode (CKE = 0) Requirements ............... 204
SPI Slave Mode (CKE = 1) Requirements ............... 205
Timer1 External Clock Requirements ...................... 194
Timer2 and Timer4 External Clock Requirements ... 195
Timer3 and Timer5 External Clock Requirements ... 195
10-bit High-Speed A/D ............................................. 212
10-bit High-Speed A/D Conversion Requirements .. 216
Hard and Soft ............................................................. 44
Sources ...................................................................... 43
Vectors ....................................................................... 44
Address Detect Mode .............................................. 121
Auto-Baud Support .................................................. 122
Baud Rate Generator (BRG) .................................... 121
Disabling .................................................................. 119
Enabling and Setup .................................................. 119
Loopback Mode ....................................................... 121
Module Overview ..................................................... 117
Operation During CPU Sleep and Idle Modes ......... 122
Receiving Data ......................................................... 120
Reception Error Handling ......................................... 120
SIMSAM = 0, ASAM = 1, SSRC = 111,
2
2
C Bus Data Requirements (Master Mode) ............ 208
C Bus Data Requirements (Slave Mode) .............. 210
In 8-bit or 9-bit Data Mode ............................... 120
Interrupt ........................................................... 120
Receive Buffer (UxRXB) .................................. 120
Framing Error (FERR) ..................................... 121
Idle Status ........................................................ 121
Parity Error (PERR) ......................................... 121
Receive Break ................................................. 121
DD
) ............................................................. 156
DD
), Case 2 ......................................... 157
dsPIC30F6010A/6015
Unit ID Locations ............................................................. 149
Universal Asynchronous Receiver
Transmitter Module (UART) ............................................. 117
W
Wake-up from Sleep ........................................................ 149
Wake-up from Sleep and Idle ............................................ 45
Watchdog Timer (WDT) ........................................... 149, 160
WWW Address ................................................................ 228
WWW, On-Line Support ...................................................... 7
Setting Up Data, Parity and Stop Bit Selections ...... 119
Transmitting Data .................................................... 119
UART1 Register Map .............................................. 123
UART2 Register Map .............................................. 123
Enabling and Disabling ............................................ 160
Operation ................................................................. 160
Receive Buffer Overrun Error (OERR Bit) ....... 120
In 8-bit Data Mode ........................................... 119
In 9-bit Data Mode ........................................... 119
Interrupt ........................................................... 120
Transmit Break ................................................ 120
Transmit Buffer (UxTXB) ................................. 119
DS70150D-page 227