IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 101
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Receiver Testbench Description
December 2010 Altera Corporation
The testbench stimulates the inputs and checks the outputs of the interfaces of the
POS-PHY Level 4 MegaCore function, demonstrating basic functionality.
The remainder of this section contains the following information about the testbench:
■
■
■
The testbench provided with the receiver variations of the POS-PHY Level 4
MegaCore function tests the following functions:
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■
■
■
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Receiver Testbench Description
Receiver Testbench Examples
Transmitter Testbench Description
Using the Avalon-MM interface, program the calendar if Asymmetric Port
Support is turned on (refer to
Synchronization of the MegaCore function with the SPI-4.2 training pattern
Data integrity from the SPI-4.2 interface through the MegaCore function variation
to the Atlantic back-end interface
Ability to send data to multiple ports
Verifies that the MegaCore function correctly drives backpressure on the SPI-4.2
interface (this test can be turned on and off)
Appendix
E)
POS-PHY Level 4 MegaCore Function User Guide
6. Testbench
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