IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 132

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

F–4
AC Timing Analysis
POS-PHY Level 4 MegaCore Function User Guide
f
f
For more information on the use of DPA in the POS-PHY Level 4 MegaCore function,
refer to
For more information on using dynamic phase alignment, refer to the following
documents:
■
■
■
Specifications for this interface allow two sets of timing relationships between the
sender and receiver: static and dynamic mode. In the static alignment mode, all data
obeys a common set of timing parameters (for example, set up and hold times with
respect to a sampling clock). In the dynamic alignment mode, a per-bit timing
relationship applies.
This section describes the timing analysis for various configurations and components.
These timing components are referenced to
timing path as related to the paths followed by the clock and data signals through the
user’s system.
data edges.
High-Speed Differential I/O Interfaces with DPA in Stratix II Devices
Stratix II Device Handbook
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices
The Need for Dynamic Phase Alignment in High-Speed FPGAs White Paper
“DPA Channel Aligner (rx_data_phy_dpa)” on page
Figure F–4 on page F–5
references the timing values to the clock and
Figure F–3 on page
Appendix F: Static and Dynamic Phase Alignment
December 2010 Altera Corporation
4–3.
F–5, which shows the
chapter of the
AC Timing Analysis