IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 102

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–2
Table 6–1. Packet Format
POS-PHY Level 4 MegaCore Function User Guide
Header byte
Extra length byte
Number byte
Payload bytes
Packet Byte
{0,0,len[5:1],ext}
{size[16:0]}
{N[7:0] ^ port_num}
{N++^ port_num}
The testbench consists of three basic modules: packet generation, user receiver
variation, and a data analyzer. All testbench modules are in the <variation name>_tb.v
file. The testbench also consists of multiple support modules for pin monitoring, clock
generation, and reset generation (refer to
generates SPI-4.2 packets. These packets are received by the receiver MegaCore
function, which processes the packets and converts them to Atlantic interface format.
Finally, the data analyzer module receives the data from the Atlantic interface and
verifies the correctness of the data with an individual monitor for each port.
Figure 6–1. Receiver Testbench
The packet generation module begins by sending the idle pattern (16'h000f) and then
the training pattern (16'h0fff,16'hf000) until the POS-PHY Level 4 receiver
MegaCore function is synchronized to the data source.
The packet generation module then begins sending packets of lengths defined by the
top-level testbench. To allow for automated packet checking, a special packet format
is used.
Packet Generation
POS-PHY Level 4
Table 6–1
Format
Reset
shows the format of each packet.
Interface
SPI-4.2
Contains information about the packet. len represents the length of
the packet if the length can be encoded in six bits. If the length is
beyond 32 bits, ext is set to indicate that the next byte in the packet
contains the length information.
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes) (optional).
Packet number (packet number begins at 'h01 and is incremented by
one for each packet) XORed with the port number.
The following bytes in the packet are incremented by one and XORed
with the port number.
Device Under Test
Generator
POS-PHY
Receiver
Variation
Level 4
Clock
Figure
6–1). The packet generation module
Description
Interface
Atlantic
December 2010 Altera Corporation
Atlantic Interface
Data Analyser
(one per port)
Pin Monitor
Receiver Testbench Description
Chapter 6: Testbench