IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 133
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 133 of 144
- Download datasheet (3Mb)
Appendix F: Static and Dynamic Phase Alignment
AC Timing Analysis
Figure F–3. Timing Analysis Model
Figure F–4. Timing Diagram
December 2010 Altera Corporation
Source
Clock
Fast
PLL
f
1
Internal Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
The calculations follow those in OIF2000.088.4, Appendix D Sample LVDS Timing
Budgets.
Random (Intrinsic)
Clock Source
For timing information on the SPI-4 Phase 2 interface, refer to the Optical
Internetworking Forum (OFI), System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1:
OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.1, October 2003.
Synchronous
Jitter
Serializer
Serializer
Channel
Jitter
Source
Clock
Data
for
for
TCCS
Buffer Distortion
Buffer Distortion
(Duty Cycle)
(Duty Cycle)
Reference Point A
Clock Placement
Skew Relative to Clock
Channel-to-Channel
SW
Data Dependent Jitter
Channel Distortion
(Deterministic)
Board Effects
Reference Point B
POS-PHY Level 4 MegaCore Function User Guide
Data Sampling Window
Jitter Attenuation/Pass-Through
plus Intrinsic Jitter
TCCS/2
Deserializer
PLL
F–5
Related parts for IP-POSPHY4
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-POSPHY4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP Thermal Transfer Printer With Peel/Present Option
Manufacturer:
BRADY
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: