IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 133
![IP CORE - POS-PHY Level 4 SPI 4.2 Interface](/photos/24/19/241943/4696146_sml.jpg)
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Appendix F: Static and Dynamic Phase Alignment
AC Timing Analysis
Figure F–3. Timing Analysis Model
Figure F–4. Timing Diagram
December 2010 Altera Corporation
Source
Clock
Fast
PLL
f
1
Internal Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
The calculations follow those in OIF2000.088.4, Appendix D Sample LVDS Timing
Budgets.
Random (Intrinsic)
Clock Source
For timing information on the SPI-4 Phase 2 interface, refer to the Optical
Internetworking Forum (OFI), System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1:
OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.1, October 2003.
Synchronous
Jitter
Serializer
Serializer
Channel
Jitter
Source
Clock
Data
for
for
TCCS
Buffer Distortion
Buffer Distortion
(Duty Cycle)
(Duty Cycle)
Reference Point A
Clock Placement
Skew Relative to Clock
Channel-to-Channel
SW
Data Dependent Jitter
Channel Distortion
(Deterministic)
Board Effects
Reference Point B
POS-PHY Level 4 MegaCore Function User Guide
Data Sampling Window
Jitter Attenuation/Pass-Through
plus Intrinsic Jitter
TCCS/2
Deserializer
PLL
F–5
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