IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 85

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Error Flagging and Handling
December 2010 Altera Corporation
The stat_ts_sync signal is deasserted when a programmed bad_level number of
calendar sequences with frame errors or DIP-2 errors is received without a good
frame. When the stat_ts_sync signal is deasserted, the transmitter stops transmitting
data on the nearest burst unit size boundary or at the next EOP, and starts sending the
training patterns continuously (refer to
Figure 5–6. Status Sync State Machine
Figure
5–6).
POS-PHY Level 4 MegaCore Function User Guide
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