IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 42

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–2
Block Description
Figure 4–1. Block Diagram—Receiver
Note to
(1) The dotted lines illustrate the clock domain separations.
POS-PHY Level 4 MegaCore Function User Guide
Figure
Data Receiver and Serial-to-Parallel Converter (rx_data_phy_altlvds)
Interface
SPI4.2
4–1:
rdclk
rsclk
1
Figure 4–1 on page 4–2
MegaCore function.
This section describes the top-level blocks of the POS-PHY Level 4 receiver MegaCore
function.
Data and control words arrive on the rdat bus, and are sampled on both edges of
rdclk. Payload and control words contain two bytes, where bit 15 is the most
significant bit (MSB) and bit 8 is the least significant bit (LSB) of the first byte, and bit
7 is the MSB and bit 0 is the LSB of the second byte.
For 128- and 64-bit variations, an ALTLVDS_RX megafunction deserializes the SPI-4.2
rdat/rctl lines into words at 1/8 or 1/4 the rdat data rate, respectively. The rdint_clk
is derived from the rdclk input pin, and is the clock that drives the internal logic
elements for the receiver.
For 32-bit (quarter-rate) variations, an ALTDDIO_IN megafunction deserializes the
SPI-4.2 rdat/rctl lines into words at 1/2 the rdat data rate.
For rates above 311 Mbps, the Stratix
include a dedicated SERDES (ALTLVDS megafunction) implemented in LVDS I/Os.
For rates below 250 Mbps, LVDS I/O pins are used.
A fast phase-locked loop (PLL) is required for the ALTLVDS SERDES.
Serial-to-Parallel
Data Receiver
Converter
Status PHY
And
(Note 1)
Status FSM
DPA Channel
Register
rdint_clk
Status
rav_clk
Aligner
shows the blocks and clocks that comprise the receiver
Processor
Status Hold
Calculator
Status
Data
®
III, Stratix II, Stratix GX, and Stratix devices
Chapter 4: Functional Description—Receiver
Buffer N
Atlantic
Buffer 0
Atlantic
December 2010 Altera Corporation
Atlantic
Interface 0
Atlantic
Interface N
rxsys_clk
Block Description