IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 34
![IP CORE - POS-PHY Level 4 SPI 4.2 Interface](/photos/24/19/241943/4696146_sml.jpg)
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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3–12
Protocol Parameters
Figure 3–4. Receiver Protocol Parameters
POS-PHY Level 4 MegaCore Function User Guide
Calendar Options
Figure 3–4 on page 3–12
Select Real-Time Programmable, so most of the protocol parameters on this tab
become input pins to the MegaCore function. These input pins allow each parameter
to be connected to a user-implemented register, and controlled at run-time.
Select Fixed Value, to enter values for the protocol parameters on this tab.
IP Toolbench then fixes these values in the MegaCore function, making the
parameters static and the input pins unavailable.
Turn on Asymmetric Port Support (only available if you select the Real-time
programmable) for the calendar to allow asymmetric weighting of calendar entries to
control the allocation of bandwidth to a given SPI-4.2 port. You must program the
calendar for the MegaCore function to produce the status channel (refer to
Appendix E, Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped
Interface).
A port with twice the calendar entries of all other ports nominally uses twice as much
bandwidth on the SPI-4.2 interface depending on the data characteristics. Ports can be
disabled by removing them from the calendar.
shows the Protocol Parameters tab.
December 2010 Altera Corporation
Chapter 3: Parameter Settings
Protocol Parameters
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