IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 115

IP CORE - POS-PHY Level 4 SPI 4.2 Interface

IP-POSPHY4

Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet

Specifications of IP-POSPHY4

Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Appendix A: Start-Up Sequence
Troubleshooting
December 2010 Altera Corporation
Issues and Tips—Miscellaneous
7. Receiver (particularly third-party receivers) detects protocol errors related to burst
8. Throughput is lower than expected. The following tips may prove useful:
Miscellaneous unexpected behavior:
length. The following tips may prove useful:
Ensure all clocks are up and operating at their specified frequencies.
Ensure all resets have been asserted, and released only after clock stabilization.
Ensure all signals connected to the MegaCore function are driven or sampled with
the appropriate clock.
Ensure all parameters are set as specified.
If the transmitter is an embedded address variation, ensure that bursts are
written into the FIFO buffer in multiples of ctl_td_burstlen, or eop
terminated.
Ensure that ctl_td_burstlen is less than the buffer size.
Understand quantization effects and choose transmitter mode (lite or non-lite),
data path width, and clock frequencies appropriate for your packet size and
throughput needs.
Ensure all clocks are operating at their specified frequencies.
Ensure transmitter queue(s) always has data, otherwise factor into expectation.
Ensure receiver queue(s) always has space, otherwise factor into expectation.
Ensure status is sent or received as expected, which includes checking
stat_ts_sync, stat_td_holb, ctl_ts_status_mode, ctl_ry_fifostatoverride,
ctl_ry_ae and ctl_ty_af.
Ensure credits (ctl_td_mb1 and ctl_td_mb2) are large enough that they do not
run out between status updates.
POS-PHY Level 4 MegaCore Function User Guide
A–5

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