IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 65

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Signals
Table 4–7. Atlantic Receive Interface (Slave Source)
Table 4–8. Atlantic FIFO Buffer Control and Status (Part 1 of 2)
December 2010 Altera Corporation
aN_arxclk
aN_arxdav
aN_arxena
aN_arxdat[n:0]
aN_arxval
aN_arxsop
aN_arxeop
aN_arxmty[n:0]
aN_arxerr
aN_arxadr[7:0]
Note to
(1) N is equal to the number of ports for the individual buffers mode; N is equal to zero for the shared buffer with embedded addressing mode.
ctl_ax_ftl[n:0]
ctl_ax_fifo_eopdav
err_aN_fifo_parityN
stat_aN_fifo_emptyN
Table
Signal
4–7:
Signal
(1)
Input
Output
Input
Output
Output
Output
Output
Output
Output
Output
Direction
aN_arxclk
Input
Input –
Static
reset
Output
Output
Direction Clock Domain
Clock Domain
aN_arxclk
Atlantic clock (one for each Atlantic interface). This input is absent
and internally connected to rxsys_clk if a single clock domain is
selected. Signals prefixed with aN_ are synchronous to this clock.
Atlantic data available (one for each Atlantic interface). Asserted when
the Atlantic FIFO buffer has at least ctl_ax_ftl bytes available to
read.
Atlantic enable (one for each Atlantic interface).
Atlantic data bus (one for each Atlantic interface). The width is set by
the Atlantic interface width parameter.
Atlantic data valid (one for each Atlantic interface).
Atlantic empty signal (one for each Atlantic interface). Number of
invalid octets on the upper bits of the Atlantic data bus (aN_arxdat).
Valid only when aN_arxeop is asserted. The width is log2(Atlantic
width/8).
Atlantic port address (one for each Atlantic interface). Only present
for the shared buffer with embedded addressing mode.
Atlantic start of packet (one for each Atlantic interface).
Atlantic end of packet (one for each Atlantic interface).
Atlantic error (one for each Atlantic interface).
(Note 1)
FIFO buffer threshold low determines when to inform the
user logic that data is available via the aN_arxdav signal.
This threshold applies to all buffers. Units are in bytes.
Only change at reset.
Assert to turn on dav when there is an end of packet
below the FTL threshold. Value applies to all Atlantic
buffers. Only change at reset.
Indicates that the FIFO buffer has detected a parity error
(one for each Atlantic buffer).
Indicates that the FIFO buffer has underflowed. Asserted
for one cycle if a buffer read fails because the buffer is
empty (one for each Atlantic interface).
Description
POS-PHY Level 4 MegaCore Function User Guide
Description
4–25