IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 123

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix D: Board Design
Design for Testability
December 2010 Altera Corporation
Spare Pins
JTAG Scan Chain
f
f
1
SPI-4.2 Status Interface
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Other Useful Debug Signals
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In addition to these transmitter signals, it may be useful to provide test points for
similar debug and status signals from the adjacent device.
The SignalProbe feature in the Quartus II software allows you to route signals inside
the device to output pins so you can view the signals on an oscilloscope or logic
analyzer, without recompiling the design.
Altera recommends that you have a set of unused FPGA pins connected to test points
or connectors for an oscilloscope or logic analyzer. If you find problems in the design,
you can easily route internal signals to these connectors or test points to accelerate
debugging.
The following are SignalProbe feature requirements:
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For more information on using the SignalProbe feature, refer to “Performing a
SignalProbe Compilation on a Design” in Quartus II Help.
Altera recommends that you make the JTAG scan chain available for the Altera
SignalTap II logic analyzer. The SignalTap II application implements a small logic
analyzer inside the FPGA, and uses memory blocks to store waveforms. The
waveforms are sent via the JTAG interface to the SignalTap waveform viewer
application, allowing you to see what is happening inside the device.
For further information, refer to
Embedded Logic
tstat[1:0]
tsclk
FPGA reset
stat_ts_sync
err_ts_dip2
err_ts_frm
trefclk
Pins for analysis must not already be assigned for use in the design, cannot be a
group or bus, and cannot have a carry or cascade fan out.
Nodes for analysis must be post-compilation, and cannot be carry-out or cascade-
out signals or groups.
Analyzer.
AN 280: Design Verification Using the SignalTap II
POS-PHY Level 4 MegaCore Function User Guide
D–3