IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 46
![IP CORE - POS-PHY Level 4 SPI 4.2 Interface](/photos/24/19/241943/4696146_sml.jpg)
IP-POSPHY4
Manufacturer Part Number
IP-POSPHY4
Description
IP CORE - POS-PHY Level 4 SPI 4.2 Interface
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-POSPHY4.pdf
(144 pages)
Specifications of IP-POSPHY4
Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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4–6
POS-PHY Level 4 MegaCore Function User Guide
Atlantic Buffers
f
f
For a more complete list of errors detected by the MegaCore function, refer to
Flagging and Handling” on page
Clock-Domain Crossing Buffer
This block instantiates a clock-domain crossing buffer called alignment buffer (ABUF)
to transfer data from the rdint_clk clock domain to the rxsys_clk clock domain. The
depth of the alignment buffer is fixed at 128; the width is equal to the MegaCore
function data path width.
For a description of the relationship between rdint_clk and rxsys_clk, refer to
“Clock Structure” on page
SOP Alignment & Atlantic Conversion
This block moves the SOP for each packet to the first-byte position on the Atlantic
interface, and aligns the data to ensure that valid data is contiguous (no IDLEs) before
sending it to the Atlantic buffer.
The Atlantic FIFO buffers provide the following features:
■
■
■
■
■
Shared Buffer with Embedded Addressing
When the shared buffer with embedded addressing mode is selected, the POS-PHY
Level 4 MegaCore function consists of the receiver processor logic and a shared FIFO
buffer with embedded addressing.
The shared buffer is a single Atlantic FIFO buffer, where for each data word a tag is
carried containing the port number. This means that the Atlantic-side logic cannot
selectively pick a port to access. Instead, data bursts from all ports are stored
collectively into this one shared physical buffer, and the ordering of the data bursts is
maintained in the order in which they were received on the SPI-4.2 bus.
Single receive slave-source Atlantic interface on the user end
Configurable buffer size
Support for crossing clock domains
Buffer status interface
■
■
■
■
Atlantic interface error checking
■
■
Overflow error indication
Underflow warning indication
Configurable FIFO buffer threshold low (FTL)
Optional end-of-packet-based data available (aN_arxdav) signal assertion
Missing or spurious SOP/EOP detection and correction
Optional overflow handling
4–10.
4–13.
Chapter 4: Functional Description—Receiver
December 2010 Altera Corporation
Block Description
“Error
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