IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 22

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–12
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Table 2–2. DLL Reconfiguration Ports Exposed at Top-Level of Controller+PHY Wrapper (Part 2 of
Table 2–3
wrapper to allow PLL reconfiguration.
Table 2–3. PLL Reconfiguration Ports Exposed at the Top-Level of Controller+PHY Wrapper
To facilitate placement and timing closure and help compensate for PLLs adjacent to
I/Os and vertical I/O overhang issues that can occur when targeting HardCopy III
and HardCopy IV devices, an additional pipeline stage is added to the write path in
the RTL when you turn on HardCopy Compatibility. The additional pipeline stage is
added in all cases, except when CAS write latency equals 2 (for DDR3) or CAS latency
equals 3 (for DDR2), where the additional pipeline stage is not required to meet
timing requirements. The additional pipeline stage does not affect the overall latency
of the controller.
hc_dll_config_dll_offset_ctrl_
offset
hc_dll_config_dll_offset_ctrl_
offsetctrlout
hc_pll_config_configupdate
hc_pll_config_phasecounter
select
hc_pll_config_phasestep
hc_pll_config_phaseupdown
hc_pll_config_scanclk
hc_pll_config_scanclkena
hc_pll_config_scandata
hc_pll_config_phasedone
hc_pll_config_scandataout
hc_pll_config_scandone
summarizes the ports exposed at the top level of the Controller and PHY
Port Name
Port Name
Input
Output
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Direction
Direction
Offset input setting for the PLL. This is a
Gray-coded offset that is added or subtracted
from the current value of the DLL’s delay
chain.
The registered and Gray-coded value of the
current delay-offset setting.
Control signal to enable PLL reconfiguration.
(Applies to RLDRAMII and QDRII only, the
phase reconfiguration feature for DDR2/3 is
included in the CSR port.)
Specifies the counter select for dynamic phase
adjustment. (Applies to RLDRAMII and QDR II
only.)
Specifies the phase step for dynamic phase
shifting. (Applies to RLDRAMII and QDR II
only.)
Specifies if the phase adjustment should be up
or down. (Applies to RLDRAMII and QDR II
only.)
PLL reconfiguration scan chain clock.
Clock enable port of the
hc_pll_config_scanclk clock.
Serial input data for the PLL reconfiguration
scan chain.
When asserted, this signal indicates to core
logic that phase adjustment is completed and
that the PLL is ready to act on a possible
second adjustment pulse.
The data output of the serial scan chain.
Asserted when the scan chain write operation
is in progress and is deasserted when the
write operation is complete.
HardCopy Migration Design Guidelines
December 2010 Altera Corporation
Description
Description
Chapter 2: Getting Started