IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 41

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Block Description
December 2010 Altera Corporation
I/O Pads
This chapter describes the PHY part of the RLDRAM II controller with UniPHY.
The PHY comprises the following major functional units:
■
■
■
■
■
■
Figure 6–1
Figure 6–1. PHY Block Diagram
The I/O pads contain all the I/O instantiations. The bulk of the UniPHY I/O circuitry
is encapsulated in the ALTDQ_DQS megafunction (ALTDQ_DQS2 for Stratix V series
devices).
I/O Pads
Reset and Clock Generation
Address and Command Datapath
Write Datapath
Read Datapath
Sequencer
External
Memory
Device
shows the PHY block diagram.
I/O Pads
6. Functional Description—UniPHY
UniPHY
Command
Generation
Datapath
Address
Datapath
Datapath
Write
Read
Reset
and
Section IV. RLDRAM II Controller with UniPHY IP User Guide
FPGA
External Memory Interface Handbook Volume 3
Sequencer
Controller
Memory
AFI to
Controller
Memory