IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 43

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Block Description
Table 6–2. Clocks—Full-Rate Designs (Part 2 of 2)
December 2010 Altera Corporation
Clock
DQS
Notes for
(1) For memory frequencies >240 MHz.
(2) For memory frequencies <=240 MHz.
(3) For parameterizations with interface width >36, pll_mem_clk and pll_write_clk are assigned to use the global network.
Table
Address and Command Datapath
6–2:
The UniPHY uses an active-low, asynchronous assert and synchronous de-assert reset
scheme. The global reset signal resets the PLL in the PHY and the rest of the system
waits in reset until after the PLL becomes locked. The number of synchronization
pipeline stages is 4.
The memory controller controls the read and write addresses and commands to meet
the memory specifications. The PHY simply passes the address and command
received from the memory controller to the memory device. The PHY circuitry is the
same for both address and command.
The address and command datapath outputs connect to the inputs of the address and
command I/Os. An ALTDDIO_OUT megafunction converts the addresses from SDR
to DDR. An ALTDDIO_OUT megafunction with an ALTIOBUF megafunction
delivers a pair of address and command clock to the memory.
Figure 6–2
registry-and- address-swapping circuitry inside the dotted box only when it is
operating in half-rate mode with odd write latency. In full-rate mode, ddio_address_h
and ddio_addesss_l are the same.
Figure 6–2. Address and Command Datapath
Source
Memory
Full
addr_cmd_clk
illustrates the address and command datapath. The controller requires the
afi_address
Clock
Rate
pll_afi_clk
90°
Phase
Local
Clock Network
Only if half-rate and odd write latency
Type
Section IV. RLDRAM II Controller with UniPHY IP User Guide
A continuous running clock from the
memory device for capturing read data.
External Memory Interface Handbook Volume 3
ddio_address_h
ddio_address_l
Description
DDIO
DDIO
6–3