IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 47

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Interfaces
Table 6–3. Sequencer States (Part 2 of 2)
Interfaces
December 2010 Altera Corporation
State
L_ADD_MARGIN
CALIB_DONE
CALIB_FAIL
The Memory Interface
1
Figure 6–5
external memory device and the controller.
Instantiating the DLL and PLL on the same level as the UniPHY eases DLL and PLL
sharing.
Figure 6–5. UniPHY Interfaces with the Controller and the External Memory
The following interfaces are on the UniPHY top-level file:
■
■
■
■
For more information on the memory interface, refer to
page
AFI
Memory interface
DLL and PLL sharing interface
OCT interface
Description
Increment latency counter by 3 (1 cycle to get the correct data, 2 more cycles of margin for run
time variations). If latency counter value is smaller than predefined ideal condition minimum,
then go to CALIB_FAIL.
Calibration is successful.
Calibration is not successful.
6–10.
Memory Interface
RUP and RDN
shows the major blocks of the UniPHY and how it interfaces with the
OCT
UniPHY Top-Level File
PLL and DLL Sharing Interface
DLL
Section IV. RLDRAM II Controller with UniPHY IP User Guide
UniPHY
External Memory Interface Handbook Volume 3
PLL
“UniPHY Signals” on
AFI
Reset Interface
6–7