IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 26

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–16
Table 2–8. Generated Directory Structure and Key Files—SOPC Builder Flow (Part 2 of 2)
Table 2–9. Generated Directory Structure and Key Files—Qsys Synthesis Flow (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
<working_dir>/
<working_dir>/
<working_dir>/
<working_dir>/
<working_dir>/
Note to
(1) <stamp> is a unique identifier determined by SOPC Builder at generation time.
<working_dir>/<system_name>/
synthesis/
<working_dir>/<system_name>/
synthesis/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
<working_dir>/<system_name>/
synthesis/submodules/
Table
Qsys Flow
Directory
Directory
2–8:
The tables in this section list the generated directory structure and key files of interest
to users, resulting from the Qsys flow
Synthesis
Table 2–9
flow with Qsys.
lists the generated directory structure and key files created by the synthesis
<system_name>.qip
<system_name>.v
<core_name>_<stamp>.v
<core_name>_<stamp>_*.v
<core_name>_<stamp>_*.sv
<core_name>_<stamp>.sdc
<core_name>_<stamp>.ppf
<core_name>_<stamp>_pin_assignments.tcl
<core_name>_<stamp>_*.tcl
<core_name>_<stamp>_readme.txt
<core_name>_<stamp>.ppf
<core_name>_<stamp>_pin_assignments.tcl
<core_name>_<stamp>_*.tcl
<core_name>_<stamp>_readme.txt
Other IP core files.
File Name‘
File Name
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Pin Planner file.
Pin constraints script to be run
after synthesis.
Other Tcl scripts.
Readme text file.
Other IP cores.
QIP which refers to all generated
files in the Qsys system synthesis
fileset.
Qsys system top-level wrapper.
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL files.
Synopsys constraints file.
Pin Planner file.
Pin constraints script to be run
after synthesis.
Other Tcl scripts.
Readme text file.
December 2010 Altera Corporation
Description
Chapter 2: Getting Started
Description
Generated Files