IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 45

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Block Description
Figure 6–4. Read Datapath
December 2010 Altera Corporation
DQ[0...n]
QKn
QK
PLL
Read Datapath
DLL
+
-
The read data is captured in the input mode ALTDQ_DQS in the I/O. The captured
data passes to the read datapath. The read datapath synchronizes read data from the
read capture clock domain to the AFI clock domain and converts data from SDR to
HDR (half-rate designs only).
In half-rate designs, the write side of the FIFO buffer should be double the size of the
read side of the FIFO buffer. The read side only reads one entry after the write side has
written into two entries, which effectively converts data from SDR to HDR. In full-rate
designs, the size of the FIFO buffer is the same for both write and read as both sides
operate at the same rate. For half-rate designs, the FIFO operates at half-rate on both
read and write sides, and contains 4 half-rate entries; for full-rate designs, the FIFO
operates at full-rate on both read and write sides, and contains 8 full-rate entries.
Figure 6–4
(DQ) returned from memory are edge-aligned; the DQS and DQSn delay chains shift
the clocks to achieve center alignment.
DQS Delay Chain
ALTDQ_DQS
illustrates the read datapath. The DQS and DQSn clocks and the read data
o
DDIO_IN
DDIO_IN_n-1
calibrated by PHY
write enable
read_capture_clk
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
data_high
data_low
FIFO
pll_afi_clk
read valid
read data
6–5