IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 49

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Interfaces
December 2010 Altera Corporation
The OCT Sharing Interface
By default, the UniPHY IP generates the required OCT control block in the top-level
RTL file for the PHY. If you want, you can instantiate this block elsewhere in your
code and feed the required termination control signals into the IP core by turning off
Master for OCT Control Block on the PHY Settings tab. If you turn off Master for
OCT Control Block, you must instantiate the OCT control block, or use another
UniPHY instance as a master, and ensure that the parallel and series termination
control bus signals are connected to the PHY.
You must create termination Control Block assignments for all calibrated input-only
pins, to designate which OCT control block to use for those pins. If the UniPHY IP is
in OCT Control Block master mode, these assignments are included in the
<variation_name>_pin_assignments.tcl file which must be run after analysis and
synthesis. If the UniPHY IP is not using OCT Control Block master mode the user
must manually create the required assignments to connect the input-only pins to the
relevant OCT control block. For RLDRAM this is just the input clock, all output and
bidirectional pins are hard coded between the pin's I/O buffer and the series and
parallel termination control signals.
Figure 6–6
Master for OCT Control Block.
Figure 6–6. PHY Architecture with Master for OCT Control Block
c
Memory Interface
You must be extremely careful when connecting clock signals to the slave.
Connecting to clocks with frequency or phase different than what the core
expects may result in hardware failures.
RUP and RDN
and
Figure
6–7, respectively, show the PHY architecture with and without
OCT
OCT
Sharing
Interface
UniPHY Top-Level File
Sharing Interface
Section IV. RLDRAM II Controller with UniPHY IP User Guide
DLL
PLL and DLL
UniPHY
PLL
External Memory Interface Handbook Volume 3
Reset Interface
AFI
6–9