IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 62
![IP CORE Renewal Of IP-RLDII/UNI](/photos/24/19/241946/4696147_sml.jpg)
IPR-RLDII/UNI
Manufacturer Part Number
IPR-RLDII/UNI
Description
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer
Altera
Datasheet
1.IP-RLDIIUNI.pdf
(76 pages)
Specifications of IPR-RLDII/UNI
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GZ, Stratix III, Stratix IV, HardCopy III
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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6–22
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
■
■
■
Ensure that the vendor-supplied memory model that you have is correct for your
memory devices.
Disconnect all signals from the default memory model and reconnect them to the
vendor-supplied memory model.
If you intend to run simulation from the Quartus II software, ensure that the .qip
file points to the vendor-supplied memory model.
Chapter 6: Functional Description—UniPHY
Using a Vendor-Specific Memory Model
December 2010 Altera Corporation
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