IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 42
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IPR-RLDII/UNI
Manufacturer Part Number
IPR-RLDII/UNI
Description
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer
Altera
Datasheet
1.IP-RLDIIUNI.pdf
(76 pages)
Specifications of IPR-RLDII/UNI
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GZ, Stratix III, Stratix IV, HardCopy III
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
6–2
Table 6–1. Clocks—Half-Rate Designs
Table 6–2. Clocks—Full-Rate Designs (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Clock
pll_afi_clk
pll_mem_clk
pll_write_clk
pll_addr_cmd_clk
DQS
Notes for
(1) For memory frequencies >240 MHz.
(2) For memory frequencies <=240 MHz.
(3) For memory frequencies >=240 MHz, for Stratix V devices only.
(4) For parameterizations with interface width >36, pll_mem_clk and pll_write_clk are assigned to use the global network.
Clock
pll_afi_clk
pll_mem_clk
pll_write_clk
pll_addr_cmd_clk
Table
Reset and Clock Generation
6–1:
The clocking operation in the PHY can be classified into two domains: the
PHY-memory domain and the PHY-AFI domain. The PHY-memory domain
interfaces with the external memory device and is always at full-rate. The PHY-AFI
domain interfaces with the memory controller and can be either a full-rate or half-rate
clock based on the choice of the controller.
half-rate designs.
Table 6–2
Source
PLL: C0
PLL: C1
PLL: C2
PLL: C3
Memory
Source
PLL: C0
PLL: C1
PLL: C2
PLL: C3
lists the clocks required for full-rate designs.
Half
Full
Full
Half
Full
Full
Full
Full
Full
Clock
Clock
Rate
Rate
0°
0°
-45°
-90°
-135°
45°
Set in wizard
(default 270°)
90°
0°
90°
0°
180°
-90°
Set in wizard
(default 225°)
(1)
(2)
(1)
Phase
Phase
(3)
(2)
(1)
(2)
(1)
(2)
Unconstrained
Dual-regional
Dual-regional
Dual-regional
Unconstrained
Dual-regional
Dual-regional
Dual-regional
Local
Clock Network
Clock Network
Type
Type
Table 6–1
(3)
(3)
(4)
(4)
Clock for AFI logic.
Output clock to memory.
Clock for write data out to memory (data is
center aligned with the delayed
pll_write_clk).
Clock for the address and command out to
memory (address and command is center
aligned with memory clock).
A continuous running clock from the
memory device for capturing read data.
Clock for AFI logic.
Output clock to memory.
Clock for write data out to memory (data is
center aligned with the delayed
pll_write_clk).
Clocks address/command out to memory.
180° gives adress and command center
aligned with memory clock; 225° produces
best overall timing results.
lists the clocks required for
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
Description
Description
Block Description