MPU-6050 INVENSENSE, MPU-6050 Datasheet - Page 34

• Manufacturer Part Number: MPU-6050
• Description: GYRO/ACCEL, 9-AXIS FUSION, PROG, I2C
• Manufacturer: INVENSENSE

Specifications of MPU-6050

• No. Of Axes: 9
• Sensor Case Style: QFN
• No. Of Pins: 24
• Supply Voltage Range: 2.5V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Interface: I2C
• Acceleration Range: ± 2g, ± 4g, ± 8g, ± 16g
• Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address
followed by an 8
or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge
signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To
acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line.
Data transmission is always terminated by the master with a STOP condition (P), thus freeing the
communications line. However, the master can generate a repeated START condition (Sr), and address
another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while
SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
To write the internal MPU-60X0 registers, the master transmits the start condition (S), followed by the I
address and the write bit (0). At the 9
transfer. Then the master puts the register address (RA) on the bus. After the MPU-60X0 acknowledges the
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK
signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last
ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the
MPU-60X0 automatically increments the register address and loads the data to the appropriate register. The
following figures show single and two-byte write sequences.
Single-Byte Write Sequence
Burst Write Sequence
Master
Slave
Master
Slave
S
S
AD+W
AD+W
th
bit, the read/write bit. The read/write bit indicates whether the master is receiving data from
ACK
ACK
MPU-6000/MPU-6050 Product Specification
RA
RA
th
ACK
ACK
clock cycle (when the clock is high), the MPU-60X0 acknowledges the
Complete I
DATA
DATA
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2
C Data Transfer
ACK
ACK
DATA
P
ACK
Document Number: PS-MPU-6000A-00
Revision: 1.0
Release Date: 11/24/2010
P
2
C