MPU-6050 INVENSENSE, MPU-6050 Datasheet - Page 35

• Manufacturer Part Number: MPU-6050
• Description: GYRO/ACCEL, 9-AXIS FUSION, PROG, I2C
• Manufacturer: INVENSENSE

Specifications of MPU-6050

• No. Of Axes: 9
• Sensor Case Style: QFN
• No. Of Pins: 24
• Supply Voltage Range: 2.5V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Interface: I2C
• Acceleration Range: ± 2g, ± 4g, ± 8g, ± 16g
• Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To read the internal MPU-60X0 registers, the master sends a start condition, followed by the I
a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the
MPU-60X0, the master transmits a start signal followed by the slave address and read bit. As a result, the
MPU-60X0 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK)
signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the
9
Single-Byte Read Sequence
Burst Read Sequence
10.4
th
Master
Slave
Master
Slave
Signal
clock cycle. The following figures show single and two-byte read sequences.
NACK
DATA
ACK
AD
RA
W
R
S
P
I
2
C Terms
S
S
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the
9
Not-Acknowledge: SDA line stays high at the 9
MPU-60X0 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
th
AD+W
AD+W
clock cycle
2
C address
ACK
ACK
MPU-6000/MPU-6050 Product Specification
RA
RA
ACK
ACK
S
S
35 of 53
AD+R
AD+R
ACK
ACK
th
clock cycle
DATA
DATA
ACK
NACK
Document Number: PS-MPU-6000A-00
Revision: 1.0
Release Date: 11/24/2010
DATA
P
NACK
2
C address and
P