ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 42

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Table 49 DACxCON Registers (Default Value = 0x100, Read/Write Access)
Name
DAC0CON
DAC1CON
DAC2CON
DAC3CON
Table 50. DAC0CON MMR Bit Designations
Bit
15:9
8
7
6
5
4
3
2
1:0
Table 51. DACxDAT Registers (Default Value = 0x00000000, Read/Write Access)
Name
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
Table 52. DACxDAT MMR Bit Designations
Bit
31:28
27:16
15:12
11:0
Value
0
1
0
0
0
0
0
0
00
01
10
11
Name
DACPD
DACBUF_LP
BYP
DACCLK
DACCLR
Mode
Rate
DACRNx
Description
Reserved.
DAC power-down. Set by the user to set DACOUTx to tristate mode.
DAC buffer low power mode. Set by the user to place DAC_BUFF into a low power mode.
DAC bypass bit.
Set this bit to bypass the DAC buffer.
Cleared to buffer the DAC output.
DAC update rate.
Set by the user to update the DAC using Timer1.
Cleared by the user to update the DAC using HCLK (core clock).
DAC clear bit.
Set by the user to enable normal DAC operation.
Cleared by the user to reset data register of the DAC to 0.
Mode bit.
Set by the user to operate on DAC normal mode and turn off the interpolator clock source. Cleared by the
user to enable the interpolation mode.
Rate bit. Set by the user to enable the interpolation clock to HCLK/16. Cleared by the user to HCLK/32.
DAC range bits.
DAC range is from AGND to the internal reference.
EXT_REF DAC range is from AGND to the external reference. See the REFCON MMR in Table 39 for details.
EXT_REF DAC range is from AGND to the external reference. See the REFCON MMR in Table 39 for more
details.
AVDD and AGND.
Description
Reserved.
12-bit data for DACx.
Extra bits for interpolation mode.
Reserved.
Address
0xFFFF0584
0xFFFF058C
0xFFFF05B4
0xFFFF05DC
Rev. 0 | Page 42 of 96
Address
0xFFFF0580
0xFFFF0588
0xFFFF05B0
0xFFFF05D8