ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 70

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Bit
4
3
2
1
0
Name
I2CSRxFO
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
Description
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
I
I
I
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit
transmission. This bit asserts once only for a transfer.
This bit is cleared after being read.
This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI
bit in I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit
transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
This bit is high if the Tx FIFO is empty when a master requests data from the slave. This bit asserts at the rising edge
of SCL during the read bit.
This bit clears in all other conditions.
2
2
2
2
C slave receive request bit.
C slave transmit request bit.
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
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