ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 75

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

Table 98. SPICON MMR Bit Designations
Bit
15:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPIOEN
SPIROW
SPIZEN
SPITMDE
SPILF
SPIWOM
SPICPO
SPICPH
SPIMEN
SPIEN
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have
been received into the FIFO.
[11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four
bytes present.
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the
Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is set, all incoming data is ignored and no interrupts are generated. If this bit is set and SPITMDE = 0, a read of the Rx
FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the Tx register. The P0.5/ CS /PLAI[10]/ADC
transfer until Tx is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
Loopback enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
Slave MISO output enable bit.
Set this bit for normal operation of MISO.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is clear.
SPIRX overflow overwrite enable.
Set by the user, the valid data in the Rx register is overwritten by the new serial byte that is received.
Cleared by the user, the new serial byte that is received is discarded.
SPI transmits zeros when Tx FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full.
LSB first transfer enable bit.
Set by the user, the LSB is transmitted first.
Cleared by the user, the MSB is transmitted first.
SPI wired or mode enable bit.
Set to 1 to enable open-drain data output enable. External pull-ups are required on data output pins.
Clear for normal output levels.
Serial clock polarity mode bit.
Set by the user, the serial clock idles high.
Cleared by the user, the serial clock idles low.
Serial clock phase mode bit.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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CONVST
pin is asserted and remains asserted for the duration of each 8-bit serial
ADuC7121