ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 45

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

IDAC MMRs
Table 53. IDAC Control Registers (Read and Write Access)
Name
IDAC0CON
IDAC1CON
IDAC2CON
IDAC3CON
IDAC4CON
TDSCON
IDAC0PULLDOWN
Table 54. IDACxCON MMR Bit Designations
Bit
15:9
8:7
6
5
Name
SFHMODE
MSBSHFEN
LSBSHFEN
Value
00
01
10
11
0
0
Address (Hex)
0xFFFF0700
0xFFFF070C
0xFFFF0718
0xFFFF0724
0xFFFF0730
0xFFFF073C
0xFFFF0744
Description
These bits are reserved.
Bit shuffling is a method of
increasing the ac precision of an
IDAC. Do not use in applications
where dc performance is
important.
Shuffle one increment at a time.
Shuffle based on an internal
counter.
Shuffle based on the input data.
Reserved.
MSB shuffle enable.
Set by the user to 1 to enable MSB
shuffling.
Set by the user to 0 to disable MSB
shuffling.
LSB shuffle enable.
Set by the user to 1 to enable LSB
shuffling.
Set by the user to 0 to disable LSB
shuffling.
REFERENCE
VOLTAGE
BUF
Default Value
0x0010
0x0010
0x0010
0x0010
0x0010
0x00
0x00
R
EXT
I
REF
LDO
3.3V
0.47µF
2.5V
Rev. 0 | Page 45 of 96
Figure 31.
Bit
4
3
2
1
0
Table 55. TDSCON MMR Bit Designations
Bit
7:3
2
1
0
C
Value
0
0
0
DAMP
Name
IDACPD
IDACCLK
IDACCLR
Mode
Reserved
PULL_DOWN
BUF
Name
Reserved
DISLR
DISINT
DISSD
Value
1
0
0
0
0
PGND
PVDD
Description
The user sets these bits to 0.
Disable low external resistance bit.
Set by the user to 0 to disable the
output current DACs if the external
resistance is lower than a trip point.
Disable thermal trigger interrupt.
Set by the user to 0 to generate an
interrupt if the temperature passes
the thermal shutdown point.
Set by the user to 0 to disable the
output current DACs when the
temperature passes a trip point.
Description
IDAC power-down bit.
Set by the user to 1 to power
down the IDAC. IDAC output is
high impedance.
Set by the user to 0 to power up
the IDAC.
IDAC update rate.
Set by the user to update the IDAC
using Timer1.
Cleared by the user to update the
IDAC using HCLK (core clock).
IDAC clear bit.
Set by the user to enable normal
IDAC operation.
Cleared by the user to reset data
register of the IDAC to 0.
Mode bit. This bit must always be
cleared.
Set this bit to 0.
I
OUT
ADuC7121