ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 68

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Table 94. I2CxSCTL MMR Bit Designations
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
Name
I2CSTXENI
I2CSRXENI
I2CSSENI
I2CNACKEN
I2CSSEN
I2CSETEN
I2CGCCLR
I2CHGCEN
I2CGCEN
Reserved
I2CSEN
Slave transmit interrupt enable bit.
Slave receive interrupt enable bit.
Description
Reserved bits.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this interrupt source.
I
Set this bit to no acknowledge the next byte in the transmission sequence.
Clear this bit to let the hardware control the acknowledge/no acknowledge sequence.
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
I
Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.
Clear this bit at all other times.
I
general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register.
If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention
from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The
ADuC7121 watches for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB
of the I2CxALT register should always be written to 1, as per the I
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
Clear to disable recognition of hardware general call commands.
I
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave
address by hardware) as the data byte, the I
command can be used to reset an entire I
address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must
take corrective action by reprogramming the device address.
Set this bit to allow the slave acknowledge I
Clear to disable recognition of general call commands.
Always set this bit to 0.
I
Set by the user to enable I
Clear to disable I
2
2
2
2
2
2
2
2
C stop condition detected interrupt enable bit.
C no acknowledge enable bit.
C slave SCL stretch enable bit.
C early transmit interrupt enable bit.
C general call status and ID clear bit.
C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a
C general call enable. Set this bit to enable the slave device to acknowledge an I
C slave enable bit.
2
C slave mode.
2
C slave mode.
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2
C system. If it receives a 0x04 (write programmable part of the slave
2
2
C interface resets as per the I
C general call commands.
2
C January 2000 bus specification.
2
Preliminary Technical Data
C bus.
2
C January 2000 bus specification. This
2
C general call, Address 0x00