CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 13

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 9. Internal Registers (continued)
Document Number: 001-24599 Rev. *F
Data Block
(continued)
Sequencer
Block
datachannel1_2
datachannel12_
1
datachannel12_
2
seqmode1
seqmode2
seqmode3
Register Name Address [6..0]
56
57
58
33
54
55
Field
[5:4]
[7:0]
[5:4]
[7:0]
[4:0]
[6:5]
[5:3]
[2]
[3]
[0]
[1]
[2]
[3]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[6]
0
0
0x00
0x00
0
0
0
0
0x00
0x00
0
1
0
0
0
0
0
0
‘10000’
‘00’
‘1’
‘0’
‘0’
“001”
0
Reset Value
Overwrite incoming ADC data by the data in the testpat
register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the testpat
register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Enables sequencer for image capture
‘1’: Master mode, integration timing is generated on-chip
‘0’: Slave mode, integration timing is controlled off-chip
through INT_TIME1, INT_TIME2 and INT_TIME3 pins
‘0’: Pipelined mode
‘1’: Triggered mode
Enables(‘1’)/disables(‘0’) subsampling
‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0
‘0’: B&W subsampling scheme: 1:0:1:0:1
Enable dual slope
Enable triple slope
Enables continued row select (that is, assert row select
during pixel read out)
Must be overwritten with‘10001’ to this register after startup,
before readout.
Number of active windows:
“00”: 1 window
“01”: 2 windows
“10”: 3 windows
“11”: 4 windows
Enables the generation of the CRC10 on the data and sync
channels
Enable readout black/grey columns
Enable column fpn calibration/enable readout dummy line
Number of frames in nondestructive read out:
“000”: invalid
“001”: one reset, one sample (default mode)
“010”: one reset, two samples
…
Controls the granularity of the timer settings (only for those
that have ‘granularity selectable’ in the description):
‘0’: Expressed in number of lines
‘1’: Expressed in clock cycles (multiplied by
2**seqmode4[3:0])
Description
CYIL2SM1300AA
Page 13 of 43
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