CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 18

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Image Sensor Timing and Readout
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the frame overhead time (FOT), and the row overhead time (ROT). The frame period is
calculated as follows:
1 kernel = 24 Pixels = 2 Timeslots = 2 Granularity clock cycles
Table 10. Frame Rate Parameters
Note For more information on FPS calculation, refer the Cypress application note AN57864.
In global shutter mode, the whole pixel array is integrated simultaneously including the dummy line for FPN correction.
Windowing
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size in the x-direction is 24 pixels (choose only
multiples of 24 as start or stop addresses). The minimum step
size in the y-direction is one line (every line can be addressed)
in normal mode, and two lines in sub sampling mode.
The section
of registers to achieve the desired ROI.
Document Number: 001-24599 Rev. *F
FOT
ROT
Nr. Lines
Nr. Pixels
Clock Period 1/63 MHz = 15.9 ns
Parameter
Sequencer and Logic
Frame Overhead Time
Row Overhead Time
Number of lines read out each frame Number of lines in ROI
Number of pixels read out each line Number of pixels in ROI
Comment
on page 11 discusses the use
Figure 11. Timing Diagram
Every channel works at
Programmable: Default
315 granularity clock cycles (5 µs at 63 MHz)
Programmable: Default 9 granularity clock cycles (143.1 ns at 63 MHz)
63 MHz
12 channels result in 756 MHz data rate
Table 11. Typical Frame Rates at 315 MHz
Resolution (X*Y)
1296x1024
1008x1000
816x600
648x480
528x512
264x256
144x128
Image
24x2
Clarification
Out Time (ms)
Frame Read
1.9760
1.5807
0.7997
0.5370
0.4887
0.1596
0.0640
0.0098
CYIL2SM1300AA
Frame Rate (fps)
102249
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