CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 9

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Sensor Architecture
Image Sensor Core
The floor plan of the architecture is shown in
transmitters and receivers. Separate modules for the SPI, clock division, and sequencer are also integrated. The image sensor of
1280 x 1024 active pixels is read out in progressive scan.
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.
The starting point of the address can be uploaded by the SPI.
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.
The 6T Pixel
To obtain the global shutter feature combined with a high
sensitivity and good parasitic light sensitivity (PLS), implement
the pixel architecture shown in
is designed with a 14 µm x 14 µm pixel pitch to meet the
specifications listed in
architecture also enables pipelined or triggered mode.
Document Number: 001-24599 Rev. *F
Table 1
Figure
24x 10-bit digital channels
12x 10-bit digital channels
and
24 analog channels
Table 2
6. This pixel architecture
Figure
on page 3. This
Figure 5. Floor Plan of the Sensor
12x LVDS outputs at 630 Msps
5. The sensor consists of a pixel array, analog front end, data block, and LVDS
Analog front end
LVDS TX and RX
1280 x 1024
Image core
Local register
Data block
31.5 Msps
31.5 Msps
63 Msps
Reset
Clk X & Clk Y
31.5 MHz
Vpix
63 MHz
Figure 6. 6T Pixel Architecture
315 MHz
Sequencer
Divider
Logic
Clock
SPI
&
Sample
Clk out
Clk in
Vmem
CYIL2SM1300AA
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