DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 12

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
12
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
PBGA
Ball #
N.C.: Not Connected.
Table 1.
G3
F3
F2
F1
Pin Assignments and Signal Descriptions (Sheet 2 of 11)
LQFP
Pin #
88
87
86
85
Symbol
A3
A2
A1
A0
I/O
DI
DI
DI
DI
1
Protected Monitoring/Address Select Inputs.
Hardware Mode
In hardware mode these pins are used to select a specific port for non
intrusive monitoring. During protection monitoring receiver 0 inputs are
internally connected to a specific transmit or receive port. Receiver 0
routes the data from the selected port to its data and clock recovery
circuits. The data on the monitor port can be routed to TTIP0/TRING0 by
activating the remote loopback for channel 0 (TCLK0 must be active in
order for this operation to take place). In addition, the recovered clock and
data can be observed at the RCLK0/RPOS0/RNEG0 outputs.
If A0-A3 are Low, the LXT386 is configured as a quad line transceiver
without monitoring capability.
Transmitter monitoring is not supported when the respective channel is set
to analog loopback mode.
Host Mode
In non-multiplexed host mode, these pins function as non-multiplexed
address pins.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No Protection Monitoring
Receiver 1
Receiver 2
Receiver 3
Reserved
Reserved
Reserved
Reserved
No Protection Monitoring
Transmitter 1
Transmitter 2
Transmitter 3
Reserved
Reserved
Reserved
Reserved
Selection
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